Throw away the infinite ladder of analog voltages and keep only two rungs — HIGH and LOW. From those two states, a handful of logic gates, and a single clock tick, the entire edifice of counters, adders, memory, and computers is built. This chapter shows how two voltage levels, combined and clocked cleverly, scale into machines that decide, count, and remember.
A floor-cleaning robot is wandering an office at 2 a.m. It has to answer one yes/no question over and over: should I drive back to the charging dock right now? The rule its designers wrote down sounds simple in English: recharge if the battery is low, OR if the sleep-timer has fired, OR if it has finished both the vacuuming task AND the waxing task.
Try to build that with the analog circuits from earlier chapters and you immediately get stuck. An op-amp adds, subtracts, integrates — it manipulates a continuous voltage. But it cannot decide. "Either A or B, but only this combination of C and D" is not arithmetic on a smooth voltage; it is a question of true and false. Analog electronics has no native notion of true and false. Digital electronics is built around exactly that.
Name the four conditions with single letters: B = battery low, T = timer fired, V = vacuuming done, W = waxing done. Each is a wire that sits at +5 V when its condition is true and at 0 V when false. The whole decision collapses into one line of Boolean algebra:
Here + means OR, · means AND, and E is the single output wire that drives "go home." Three logic gates — two ORs and one AND — wired to those four sensor lines reproduce the English sentence exactly. And because there are only four one-bit inputs, there are only 24 = 16 possible situations the robot can ever be in. We can write down what E does in all sixteen of them in a single table and be certain we have covered every case. No analog circuit gives you that kind of total, provable coverage.
E = (B + T) + V·W is the seed. Tab 1 explains why two voltage levels. Tabs 2–3 encode numbers in those levels. Tab 4 builds the gates that compute OR and AND. Tabs 5–7 shrink expressions like this to the fewest gates. Tabs 8–9 wire gates into adders and selectors. Tab 10 adds memory so the robot can remember it already started heading home. Everything grows out of this little decision.Click the four sensor switches to set B, T, V, W. The gate network lights up and the output lamp E tells the robot whether to recharge. Watch how either branch alone is enough, and how V and W must both be on for the AND branch to fire.
Two worked situations from the brief. With B=0, T=0, V=1, W=1: the OR branch (B+T) is 0, but V·W = 1·1 = 1, so E = 0 + 1 = 1 — recharge, because both jobs are done. Now drop W to 0: V·W = 1·0 = 0 and B+T is still 0, so E = 0 — do not recharge, because waxing isn't finished and nothing else is urgent. One flipped bit changes the robot's entire behaviour, and the table predicts it.
Why throw away the rich continuum of analog voltages and keep just two values? Because noise. Send a 3.7 V analog signal down a long wire next to a switching motor and it arrives as 3.4 V or 4.0 V — and you have no way to know it drifted. But agree in advance that anything above 2.5 V means "1" and anything below 2.1 V means "0", and a 3.7 V signal that sags to 3.4 V is still, unmistakably, a 1. Digital logic trades resolution for immunity: it can regenerate a perfect signal from a battered one, which is exactly what lets information travel and be stored without rotting.
A digital wire therefore lives in one of two states. HIGH is the supply rail, near +5 V on classic logic, representing logic 1 / true / ON. LOW is ground, near 0 V, representing logic 0 / false / OFF. The two states map onto a transistor that is either saturated (fully ON, output pulled to ground) or cut off (fully OFF, output pulled to the rail) — the very switch behaviour you met in the transistor chapters. Logic ICs simply package thousands of such switches.
Real gates do not demand exactly 5 V or exactly 0 V. The popular 74HC CMOS family running on a 5 V supply guarantees that any input above about 3.15 V (roughly 0.7×VCC) reads as HIGH and anything below about 1.35 V (0.3×VCC) reads as LOW. The gap between is the forbidden region — a signal lingering there is ambiguous and slow. HC parts happily run anywhere from 2 V to 6 V, scaling their thresholds with the supply, which is why the same chip works in a 3.3 V microcontroller system and a 5 V one.
Worked example. A 74HC gate on VCC=5 V. The input is 3.4 V. Threshold for HIGH is 0.7×5 = 3.5 V — so 3.4 V actually sits just inside the forbidden region and is not guaranteed to read as 1. Add 0.3 V of margin (raise it to 3.7 V) and it is safely HIGH. Drop the supply to 3.3 V and the HIGH threshold falls to 0.7×3.3 ≈ 2.31 V, so that same 3.4 V signal is now comfortably HIGH. Thresholds track the supply.
Drag the supply voltage and the input voltage. The bands for LOW, forbidden, and HIGH scale with VCC. The readout tells you how the input is interpreted and how much noise margin remains.
Two voltage levels per wire means each wire holds exactly one bit — one binary digit, a 0 or a 1. To represent anything bigger than true/false, we line up several wires and read them as a number in base 2. The idea is identical to decimal place-value; only the base changes.
In decimal, 305 means 3×102 + 0×101 + 5×100. In binary, each place is a power of 2 instead of 10. The rightmost bit is the least significant bit (LSB), worth 20=1; the leftmost is the most significant bit (MSB). To convert binary → decimal, just add the place values where a 1 sits:
Going the other way, repeatedly divide by 2 and collect the remainders — then read them bottom-up. Worked example A: 1310.
Read the remainders from the last division up to the first: 1, 1, 0, 1 = 11012. Check by adding place values: 8 + 4 + 0 + 1 = 13. Correct.
Worked example B: 10910. Dividing repeatedly gives remainders 1,0,1,1,0,1,1 from bottom to top, i.e. 11011012. Verify: 64 + 32 + 0 + 8 + 4 + 0 + 1 = 64+32+8+4+1 = 109. Notice it took 7 bits, because 26=64 ≤ 109 < 128 = 27.
Each added wire doubles the count of distinct patterns, so n bits encode 2n values, from 0 to 2n−1. Four bits give 24=16 values (0–15), one byte of eight bits gives 28=256 values (0–255). This is the same "16 situations" the robot's four inputs produced — combinations of bits and counting values are the same arithmetic seen from two angles.
Click any of the 8 bit cells to toggle it; the decimal and hex readouts update live. Press Count +1 to ripple through 0–255 and watch the carry cascade; it rolls over from 11111111 back to 00000000.
Binary is honest but tedious: 11011012 is hard to read and easy to mistype. The fix is to group bits into chunks that map to a single compact symbol. Two groupings dominate digital design: hexadecimal (groups of 4 bits) and BCD (one decimal digit per 4 bits).
Four bits hold 24=16 patterns, exactly the 16 digits of base 16: 0–9 then A,B,C,D,E,F for ten through fifteen. So F = 15, the all-ones nibble 1111. Conversion is mechanical: slice the binary into 4-bit groups from the right, translate each group. From example A, 11012 → 8+4+1 = 13 → D16. So 1310 = 11012 = D16 — three faces of one number.
A whole byte (8 bits) becomes just two hex digits — which is why register dumps, colour codes (#6D...), and memory addresses are written in hex. It is binary you can actually read aloud.
Binary-coded decimal encodes each decimal digit separately in its own 4 bits. The number 109 in BCD is three nibbles: 0001 0000 1001 (1, 0, 9). Note this is not the same bits as pure binary 109 (1101101). BCD wastes bit patterns — the six codes 1010 through 1111 are illegal — but it earns its keep wherever humans read digits directly: seven-segment displays, digital clocks, voltmeters. The 7447 chip takes a BCD nibble and drives the seven segments of a numeric display.
Drag the decimal value 0–255 and watch its binary, hex, and BCD representations side by side. The 4-bit nibbles are shaded so you can see each hex digit map to one group of four bits.
A logic gate is a circuit whose output is a fixed Boolean function of its inputs. Each gate is fully described by its truth table: a row for every input combination, listing the output. Two binary inputs give 22=4 rows. Master these seven gates and you can build any digital circuit that exists.
NOT (inverter, 7404): one input, output is its opposite. Y = ¬A.
AND (7408): output HIGH only when all inputs HIGH. Y = A·B.
OR (7432): output HIGH when any input HIGH. Y = A+B.
NAND (7400): AND then NOT — LOW only when both inputs HIGH. Y = ¬(A·B).
NOR (7402): OR then NOT — HIGH only when both inputs LOW. Y = ¬(A+B).
XOR (7486): exclusive-OR, HIGH when inputs differ. Y = A⊕B.
XNOR: HIGH when inputs are equal — the equality detector. Y = ¬(A⊕B).
Two gates deserve special respect. NAND and NOR are universal: any logic function whatsoever can be built from NAND gates alone (or NOR gates alone). That is why the humble 7400 quad-NAND is the most-used logic chip ever made — a bag of NANDs is a complete logic toolkit.
Worked example: NAND. NAND outputs LOW only when both inputs are HIGH. Rows for A,B: (0,0)→1, (0,1)→1, (1,0)→1, (1,1)→0. Compare XOR on the same inputs: (0,0)→0, (0,1)→1, (1,0)→1, (1,1)→0 — HIGH only when the bits disagree. XOR is the workhorse of the adders in Tab 8, because 1⊕1 = 0 is binary addition without the carry.
Pick a gate, then click the A and B input switches. The output lamp lights when the output is HIGH, and the matching row of the gate's truth table highlights. Step through all four input rows and watch the output column emerge.
A gate network is an algebraic expression. Wire the robot's three gates and you have literally drawn E = (B + T) + V·W. The power of writing logic as algebra is that we can manipulate the expression — simplify it, factor it, prove two circuits equivalent — using a small set of identities, before we ever pick up a soldering iron. Fewer terms means fewer gates means cheaper, faster, cooler circuits.
Boolean algebra has three operations: AND (·), OR (+), and NOT (overbar). The variables and results are restricted to {0,1}. Here are the load-bearing identities, each provable by checking the (very short) truth table:
| Identity | Rule | What it says |
|---|---|---|
| OR with 0 / 1 | A+0 = A A+1 = 1 | OR-ing 0 changes nothing; OR-ing 1 forces HIGH |
| AND with 0 / 1 | A·0 = 0 A·1 = A | AND-ing 0 forces LOW; AND-ing 1 changes nothing |
| Complements | A+Á = 1 A·Á = 0 | A or not-A is always true; both at once never |
| Double negation | ¬¬A = A | Inverting twice returns the original |
| Absorption | A + A·B = A | The A·B term is redundant — A alone covers it |
| Distributive | A·(B+C) = A·B + A·C | Factor and expand just like ordinary algebra |
(Á stands for "not A", the overbar.) Absorption is the most satisfying: A + A·B = A. If A is true the whole thing is true regardless of B, and if A is false then A·B is also false — so B never matters. Two gates collapse to a wire.
Worked simplification. Suppose a tangle of conditions gives Y = A·B + A·&Bacute; (read: A-and-B OR A-and-not-B). Factor out A using the distributive law: Y = A·(B + &Bacute;). But B + &Bacute; = 1 (complement rule), and A·1 = A. So Y = A. A two-gate, two-AND-plus-one-OR circuit reduces to a bare wire to A. That is the entire game of logic minimization, and Karnaugh maps (Tab 7) automate it.
Pick an identity. The widget builds the full truth table for both sides and shades any row where they disagree (there will be none). Toggle the inputs to spotlight a row.
One pair of identities is so important it gets its own tab. De Morgan's theorems tell you how a NOT distributes over AND and OR — and in doing so they let you trade any AND for an OR (and vice versa) at the cost of some inverters. This is the secret to building everything from universal NAND gates.
In words: "NOT (A and B)" equals "not-A OR not-B", and "NOT (A or B)" equals "not-A AND not-B". The pattern: break the bar, and flip the operation. A NOT crossing a gate turns AND into OR and OR into AND. Verify the first on the row A=1,B=1: left side ¬(1·1) = ¬1 = 0; right side Á+&Bacute; = 0+0 = 0. They match, and you can check the other three rows the same way.
On a schematic, a NOT is drawn as a little circle (a "bubble") on a gate's input or output. De Morgan in pictorial form is bubble-pushing: slide a bubble through a gate and the gate changes shape (AND↔OR), leaving bubbles on the other side. A NAND (AND with an output bubble) is therefore identical to an OR fed by two inverted inputs:
This is why NAND is universal and why designers convert AND-OR logic into all-NAND or all-NOR networks: a uniform gate type is cheaper to manufacture and route. The 4011 (quad NAND) and 4001 (quad NOR) CMOS parts exist precisely because one universal gate per chip suffices.
Worked example. A safety interlock should turn a machine OFF unless guard A and guard B are both closed — i.e. Run = A·B, so Stop = ¬(A·B). By De Morgan, Stop = Á + &Bacute;: stop if guard A is open OR guard B is open. Both descriptions are the same circuit; the De Morgan form maps directly onto two "guard-open" sensors feeding an OR, which is often the more natural way to wire the sensors.
Press Push Bubble to morph a NAND gate into its De Morgan twin (OR with inverted inputs) and back. Toggle A and B to confirm both forms give the identical output on every input combination.
Algebra simplifies logic, but spotting which identity to apply takes practice and luck. The Karnaugh map (K-map) turns minimization into a visual puzzle anyone can solve. It is a truth table redrawn as a grid, arranged so that physically adjacent cells differ in exactly one input bit. Adjacent 1s can then be looped together, and each loop erases the variable that changes across it.
The clever ingredient is the row/column ordering: 00, 01, 11, 10 — Gray code, where neighbours differ by one bit. That ordering (not 00,01,10,11) is what makes geometric adjacency equal logical adjacency, so a rectangle of 1s corresponds to a single product term.
Worked example. Take a function of A,B that is 1 for (A,B) = (1,0) and (1,1), and 0 otherwise. In the K-map those two 1s sit in the A=1 row, columns B=0 and B=1. Loop both: across the loop, A stays 1 while B changes — so B drops out and the loop is just A. The minimized function is Y = A, the same result Tab 5 got algebraically from A·B + A·&Bacute;, but read straight off the picture in two seconds.
Click the truth-table outputs to flip each row's 0/1. The 3-variable K-map fills in (Gray-code ordered), the solver finds the largest loops, and prints the minimized sum-of-products plus the gate count saved versus the raw expression.
Gates so far have decided; now let them compute. Combinational blocks wire many gates into reusable functions, and the first one every machine needs is binary addition. Adding two bits, you discover the two halves of arithmetic: a sum bit and a carry bit.
Add two single bits A and B. 0+0=0, 0+1=1, 1+0=1, and 1+1 = 102 — sum 0, carry 1. The sum is HIGH when the bits differ (that is XOR) and the carry is HIGH only when both are 1 (that is AND):
One XOR and one AND — that is a half-adder. It cannot accept a carry coming in from a lower column, so it is only good for the rightmost bit.
To add column by column we need a carry input Cin too. The full-adder adds three bits A, B, Cin:
Worked example: 1 + 1 + 1. Sum: 1⊕1⊕1 = (1⊕1)⊕1 = 0⊕1 = 1. Carry: A·B + Cin·(A⊕B) = 1·1 + 1·(1⊕1) = 1 + 1·0 = 1 + 0 = 1. So Σ=1, Cout=1, meaning 1+1+1 = 112 = 3 in decimal. Exactly right.
Stack four full-adders, feeding each stage's Cout into the next stage's Cin, and you have a 4-bit ripple-carry adder — the real-silicon 74LS283. Its name "ripple" is also its flaw: stage 3's answer waits for the carry to propagate through stages 0,1,2 first, so delay grows with bit-width. Fast machines use carry-lookahead logic to predict the carries in parallel, but the ripple adder is the honest, intuitive starting point.
Set the two 4-bit numbers A and B with the bit buttons. Each full-adder stage shows its Σ and carry; the carry ripples left to right. The 5-bit result (with final carry-out) and the decimal check appear at the bottom.
Two more combinational workhorses let us route and address data. A multiplexer (mux) is a digital rotary switch: it picks one of several data inputs and forwards it to a single output, chosen by a few select lines. A decoder does the inverse: it takes an n-bit address and activates exactly one of 2n output lines.
A 2-to-1 mux has data inputs D0, D1, one select line S, and output Y. The Boolean expression is:
When S=0 the Ś term passes D0; when S=1 the S term passes D1. Scale up: a 74151 is an 8-to-1 mux, choosing among D0..D7 with three select bits (23=8). Muxes let many signals share one wire (time-multiplexing) and can even implement arbitrary logic functions by wiring the data inputs to 0s and 1s from a truth table.
A 1-of-n decoder asserts a single output line per input code. A 3-to-8 decoder (the 74LS138) takes a 3-bit address and drives exactly one of its 8 outputs. Worked example: address = 1012 = 5, so output line Y5 activates and the other seven stay idle. Decoders are how a CPU selects which memory chip or peripheral responds to an address — the address bits decode to one "chip-select" line. The 7447 is a specialized decoder turning a BCD nibble into the seven-segment pattern for a digit.
Set the 3-bit select/address with the buttons. Top: the mux highlights which data input is routed to Y. Bottom: the decoder lights the single active output line. Toggle the 8 data bits to see the selected value appear at the mux output.
Every circuit so far is combinational: the output is a pure function of the present inputs, with no memory of the past. But the robot needs memory — once it decides to head home, it should stay heading home even if the sensor flickers. Memory means a circuit whose output depends on its history, and history needs feedback. Add feedback to gates and you get sequential logic.
Cross-couple two NOR gates — each one's output feeds the other's input — and you get a set-reset (SR) latch, the simplest 1-bit memory. Set (S=1) forces the stored bit Q to 1; Reset (R=1) forces it to 0; with both inputs 0 it holds whatever it last stored. The catch: S=R=1 is forbidden, because it drives both outputs to the same illegal state and the latch settles unpredictably when the inputs release.
| S | R | Action | Q next |
|---|---|---|---|
| 0 | 0 | Hold | Q (unchanged) |
| 0 | 1 | Reset | 0 |
| 1 | 0 | Set | 1 |
| 1 | 1 | Forbidden | illegal |
The D flip-flop fixes both problems. It has a data input D and a clock input. On the rising edge of the clock, it captures whatever D is at that instant and holds it until the next edge — "Q follows D, but only at the tick." There is no forbidden combination, and crucially every flip-flop in a system samples on the same clock edge, so the whole machine advances in lockstep. This is the heartbeat of synchronous digital systems. The JK flip-flop adds one more trick: J=K=1 makes Q toggle on each edge, which is the key to counters.
Chain toggling flip-flops and each stage divides the clock frequency by two, producing a binary count. Worked example: a 3-bit counter steps 000→001→010→011→100→101→110→111→000, cycling through all 8 states then rolling over. The LSB toggles every clock; the next bit toggles half as often; the MSB an eighth as often — so a counter is also a chain of frequency dividers. Real parts: the 7493 ripple counter, the 7490 decade (divide-by-10) counter, the synchronous 74163. A clock from a 555 astable or a crystal, with period T = 1/f, drives them all.
Toggle D high or low, then press Clock Tick to send a rising edge. Q grabs the value of D at that edge and holds it — changing D between ticks does nothing until the next edge. The waveform records D, the clock, and Q over time.
Digital logic lives in a world of clean 0s and 1s, but the physical world — temperature, sound, light, motor position — is analog. The two bridges between them close this chapter: the ADC (analog-to-digital converter) samples a continuous voltage into a binary number, and the DAC (digital-to-analog converter) turns a binary number back into a voltage.
Both are governed by one number: resolution. An n-bit converter splits its full-scale range into 2n equal steps, so the smallest voltage it can resolve is one step:
Worked example: an 8-bit DAC over 0–15 V. Step = 15 V / 28 = 15/256 ≈ 0.0586 V per step. The code 100000002 = 128 produces 128×0.0586 ≈ 7.5 V — half scale, exactly as the MSB suggests. The classic DAC0808 uses an R/2R resistor ladder to weight each bit; more bits mean finer steps and a smoother reconstruction of the original analog signal. This is the round trip: analog → ADC → digital processing → DAC → analog, which underlies every digital audio player, sensor system, and microcontroller (Chapter 13).
| Concept | Core relation | Worked anchor |
|---|---|---|
| Logic levels | VIH≈0.7VCC, VIL≈0.3VCC | 74HC@5V: HIGH >3.5V, LOW <1.5V |
| Binary→decimal | N = ∑ bi·2i | 111002 = 16+8+4 = 28 |
| Decimal→binary | repeated ÷2, remainders bottom-up | 13 → 11012 = D16 |
| Capacity | n bits → 2n values | 8 bits → 256 (0–255) |
| Robot decision | E = (B+T) + V·W | V=W=1 → E=1; W=0 → E=0 |
| De Morgan | ¬(A·B)=Á+&Bacute;, ¬(A+B)=Á·&Bacute; | basis of bubble-pushing |
| Absorption | A + A·B = A | A·B+A·&Bacute; = A |
| Half-adder | Σ=A⊕B, Cout=A·B | 1+1 = 102 |
| Full-adder | Σ=A⊕B⊕Cin, Cout=AB+Cin(A⊕B) | 1+1+1 = 112 = 3 |
| Multiplexer | Y = ŚD0 + S·D1 | 74151 = 8-to-1 |
| Decoder | n-bit → 1-of-2n | 74138: 101→Y5 |
| D flip-flop | Q ← D on rising clock edge | no forbidden state |
| Counter | each stage ÷2; n stages → 2n states | 3-bit: 000…111→000 |
| Clock | T = 1/f | from 555 astable or crystal |
| ADC/DAC | step = VFS / 2n | 8-bit, 15V → 0.0586 V/step |
Drag the 8-bit input code 0–255 over a 0–15 V full scale. The output staircase shows the quantized voltage; the readout gives the exact step size and the produced voltage. Notice code 128 lands at half scale.
You started with a robot that had to make one yes/no decision. You end holding the full vocabulary — bits, gates, Boolean algebra, adders, memory — from which every computer is assembled. Chapter 13 hands all of it to software running on a microcontroller.